Altium

Design Rule Verification Report

Date: 17.09.2021
Time: 12:05:18
Elapsed Time: 00:00:02
Filename: C:\Users\ra9ucn\Documents\AD21\UA3REO\FRONT-UNIT-3.5\FRONT-UNIT-3.5.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Clearance Constraint (Gap=0.203mm) (OnLayer('Top Layer')),(All) 0
Clearance Constraint (Gap=0.203mm) (OnLayer('Bottom Layer')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.089mm) (Max=2.54mm) (Preferred=0.381mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.076mm) (All) 0
Hole Size Constraint (Min=0.486mm) (Max=21mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All) 0
Silk to Silk (Clearance=0.01mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (All) 0
Room FRONT-UNIT-3.5 (Bounding Region = (52.719mm, 53.862mm, 240.519mm, 131.662mm) (InComponentClass('FRONT-UNIT-3.5')) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 0